\doxysection{core\+\_\+cm4.\+h}
\hypertarget{core__cm4_8h_source}{}\label{core__cm4_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_cm4.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_cm4.h}}
\mbox{\hyperlink{core__cm4_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00008\ \textcolor{comment}{\ *\ Copyright\ (c)\ 2009-\/2019\ Arm\ Limited.\ All\ rights\ reserved.}}
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\DoxyCodeLine{00491\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTSET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00492\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTSET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSTSET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00494\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTCLR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00495\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTCLR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSTCLR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00497\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPREEMPT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 23U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00498\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPREEMPT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_ISRPREEMPT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00500\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPENDING\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00501\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPENDING\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_ISRPENDING\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00503\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTPENDING\_Pos\ \ \ \ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00504\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTPENDING\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_ICSR\_VECTPENDING\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00507\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_RETTOBASE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_RETTOBASE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00509\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTACTIVE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00513\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00514\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFFFFUL\ <<\ SCB\_VTOR\_TBLOFF\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00517\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00518\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_AIRCR\_VECTKEY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00520\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEYSTAT\_Pos\ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00521\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEYSTAT\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_AIRCR\_VECTKEYSTAT\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00523\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_ENDIANESS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 15U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00524\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_ENDIANESS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_ENDIANESS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00526\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00527\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_AIRCR\_PRIGROUP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00529\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Pos\ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00530\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_SYSRESETREQ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00532\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTCLRACTIVE\_Pos\ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00543\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPDEEP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00552\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00553\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_BFHFNMIGN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00555\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DIV\_0\_TRP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00562\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_USERSETMPEND\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_USERSETMPEND\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00581\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00584\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MEMFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00590\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SYSTICKACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SYSTICKACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00593\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_PENDSVACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_PENDSVACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00595\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00596\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MONITORACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00598\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00605\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00607\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00611\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_USGFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00612\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_USGFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_CFSR\_USGFAULTSR\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00614\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BUSFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00615\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BUSFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ SCB\_CFSR\_BUSFAULTSR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00617\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MEMFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00618\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MEMFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ SCB\_CFSR\_MEMFAULTSR\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00620\ \textcolor{comment}{/*\ MemManage\ Fault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00621\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MMARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 7U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00622\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MMARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MMARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00624\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MLSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 5U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00625\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MLSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MLSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00627\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00628\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00630\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MUNSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00631\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MUNSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MUNSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00633\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DACCVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00634\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DACCVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_DACCVIOL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00636\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IACCVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00637\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IACCVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CFSR\_IACCVIOL\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00639\ \textcolor{comment}{/*\ BusFault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00640\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BFARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 7U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00641\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BFARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_BFARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00643\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_LSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 5U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00644\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_LSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_LSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00646\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00647\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_STKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00649\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00650\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00652\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IMPRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 2U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00653\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IMPRECISERR\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_IMPRECISERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00655\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_PRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00656\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_PRECISERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_PRECISERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00658\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IBUSERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00659\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IBUSERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_IBUSERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00662\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DIVBYZERO\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 9U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00663\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DIVBYZERO\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_DIVBYZERO\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00665\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNALIGNED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 8U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00666\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNALIGNED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNALIGNED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00668\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_NOCP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00669\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_NOCP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_NOCP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00671\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVPC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 2U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00672\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVPC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_INVPC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00674\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVSTATE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00675\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVSTATE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_INVSTATE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00677\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNDEFINSTR\_Pos\ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00678\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNDEFINSTR\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNDEFINSTR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00681\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_DEBUGEVT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00682\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_DEBUGEVT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_DEBUGEVT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00684\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_FORCED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00685\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_FORCED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_FORCED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00687\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_VECTTBL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00688\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_VECTTBL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_VECTTBL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00691\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_EXTERNAL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00692\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_EXTERNAL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_EXTERNAL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00694\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_VCATCH\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00695\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_VCATCH\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_VCATCH\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00697\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_DWTTRAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00698\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_DWTTRAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_DWTTRAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00700\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_BKPT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00884\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_Present\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ ITM\_LSR\_Present\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00904\ \ \ \_\_IOM\ uint32\_t\ EXCCNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00905\ \ \ \_\_IOM\ uint32\_t\ SLEEPCNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00906\ \ \ \_\_IOM\ uint32\_t\ LSUCNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00907\ \ \ \_\_IOM\ uint32\_t\ FOLDCNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00908\ \ \ \_\_IM\ \ uint32\_t\ PCSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00909\ \ \ \_\_IOM\ uint32\_t\ COMP0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00910\ \ \ \_\_IOM\ uint32\_t\ MASK0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00911\ \ \ \_\_IOM\ uint32\_t\ FUNCTION0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00912\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1U];}
\DoxyCodeLine{00913\ \ \ \_\_IOM\ uint32\_t\ COMP1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00914\ \ \ \_\_IOM\ uint32\_t\ MASK1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00915\ \ \ \_\_IOM\ uint32\_t\ FUNCTION1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00916\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[1U];}
\DoxyCodeLine{00917\ \ \ \_\_IOM\ uint32\_t\ COMP2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00918\ \ \ \_\_IOM\ uint32\_t\ MASK2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00919\ \ \ \_\_IOM\ uint32\_t\ FUNCTION2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{00923\ \ \ \_\_IOM\ uint32\_t\ FUNCTION3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{00926\ \textcolor{comment}{/*\ DWT\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00927\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NUMCOMP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00928\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NUMCOMP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_NUMCOMP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00930\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOTRCPKT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00931\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOTRCPKT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOTRCPKT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00933\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOEXTTRIG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00934\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOEXTTRIG\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOEXTTRIG\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00936\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOCYCCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00937\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOCYCCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOCYCCNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00939\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOPRFCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00940\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOPRFCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOPRFCNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00942\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00943\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00945\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 21U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00946\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_FOLDEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00948\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00949\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_LSUEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00951\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00952\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_SLEEPEVTENA\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00954\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00955\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00956\ }
\DoxyCodeLine{00957\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00958\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CPIEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00960\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00961\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCTRCENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00963\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00964\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_PCSAMPLENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00966\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00967\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_CTRL\_SYNCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00969\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00970\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00972\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00973\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTINIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00975\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00976\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTPRESET\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00978\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00979\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ DWT\_CTRL\_CYCCNTENA\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00981\ \textcolor{comment}{/*\ DWT\ CPI\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00982\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00983\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_CPICNT\_CPICNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00985\ \textcolor{comment}{/*\ DWT\ Exception\ Overhead\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00986\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00987\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_EXCCNT\_EXCCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00989\ \textcolor{comment}{/*\ DWT\ Sleep\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00990\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00991\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00993\ \textcolor{comment}{/*\ DWT\ LSU\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00994\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00995\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_LSUCNT\_LSUCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00996\ }
\DoxyCodeLine{00997\ \textcolor{comment}{/*\ DWT\ Folded-\/instruction\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{00998\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00999\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_FOLDCNT\_FOLDCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01001\ \textcolor{comment}{/*\ DWT\ Comparator\ Mask\ Register\ Definitions\ */}}
\DoxyCodeLine{01002\ \textcolor{preprocessor}{\#define\ DWT\_MASK\_MASK\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01003\ \textcolor{preprocessor}{\#define\ DWT\_MASK\_MASK\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ }\textcolor{comment}{/*<<\ DWT\_MASK\_MASK\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01006\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCHED\_Pos\ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01009\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR1\_Pos\ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01010\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR1\_Msk\ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_FUNCTION\_DATAVADDR1\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01012\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR0\_Pos\ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01013\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR0\_Msk\ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_FUNCTION\_DATAVADDR0\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01015\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Pos\ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01016\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Msk\ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_FUNCTION\_DATAVSIZE\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01018\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_LNK1ENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01019\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_LNK1ENA\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_LNK1ENA\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01021\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVMATCH\_Pos\ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01022\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVMATCH\_Msk\ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_DATAVMATCH\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01024\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_CYCMATCH\_Pos\ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01025\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_CYCMATCH\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_CYCMATCH\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01027\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_EMITRANGE\_Pos\ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01028\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_EMITRANGE\_Msk\ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_EMITRANGE\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01030\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_FUNCTION\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01031\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_FUNCTION\_Msk\ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ DWT\_FUNCTION\_FUNCTION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01032\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_DWT\ */}}
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\DoxyCodeLine{01046\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
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\DoxyCodeLine{01049\ \ \ \_\_IOM\ uint32\_t\ CSPSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{01052\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[55U];}
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\DoxyCodeLine{01056\ \ \ \_\_IOM\ uint32\_t\ FFCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01057\ \ \ \_\_IM\ \ uint32\_t\ FSCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01058\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[759U];}
\DoxyCodeLine{01059\ \ \ \_\_IM\ \ uint32\_t\ TRIGGER;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01060\ \ \ \_\_IM\ \ uint32\_t\ FIFO0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01061\ \ \ \_\_IM\ \ uint32\_t\ ITATBCTR2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01062\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[1U];}
\DoxyCodeLine{01063\ \ \ \_\_IM\ \ uint32\_t\ ITATBCTR0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01064\ \ \ \_\_IM\ \ uint32\_t\ FIFO1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01065\ \ \ \_\_IOM\ uint32\_t\ ITCTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01066\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[39U];}
\DoxyCodeLine{01067\ \ \ \_\_IOM\ uint32\_t\ CLAIMSET;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01068\ \ \ \_\_IOM\ uint32\_t\ CLAIMCLR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01069\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED7[8U];}
\DoxyCodeLine{01070\ \ \ \_\_IM\ \ uint32\_t\ DEVID;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01071\ \ \ \_\_IM\ \ uint32\_t\ DEVTYPE;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{01075\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01076\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFUL\ }\textcolor{comment}{/*<<\ TPI\_ACPR\_PRESCALER\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01078\ \textcolor{comment}{/*\ TPI\ Selected\ Pin\ Protocol\ Register\ Definitions\ */}}
\DoxyCodeLine{01079\ \textcolor{preprocessor}{\#define\ TPI\_SPPR\_TXMODE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01080\ \textcolor{preprocessor}{\#define\ TPI\_SPPR\_TXMODE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ }\textcolor{comment}{/*<<\ TPI\_SPPR\_TXMODE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01082\ \textcolor{comment}{/*\ TPI\ Formatter\ and\ Flush\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01083\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtNonStop\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01084\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtNonStop\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_FtNonStop\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01086\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_TCPresent\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01087\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_TCPresent\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_TCPresent\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01089\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtStopped\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01090\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtStopped\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_FtStopped\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01092\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FlInProg\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01093\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FlInProg\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_FFSR\_FlInProg\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01096\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_TrigIn\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01097\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_TrigIn\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFCR\_TrigIn\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01099\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_EnFCont\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01100\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_EnFCont\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFCR\_EnFCont\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01101\ }
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\DoxyCodeLine{01103\ \textcolor{preprocessor}{\#define\ TPI\_TRIGGER\_TRIGGER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01104\ \textcolor{preprocessor}{\#define\ TPI\_TRIGGER\_TRIGGER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_TRIGGER\_TRIGGER\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01107\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01108\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FIFO0\_ITM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01110\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_bytecount\_Pos\ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01111\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO0\_ITM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01113\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01114\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FIFO0\_ETM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01116\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_bytecount\_Pos\ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01117\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO0\_ETM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01119\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM2\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01120\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM2\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO0\_ETM2\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01122\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM1\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01123\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM1\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO0\_ETM1\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01125\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM0\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01126\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM0\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ TPI\_FIFO0\_ETM0\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01129\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY2\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01130\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY2\_Msk\ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_ITATBCTR2\_ATREADY2\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01132\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY1\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01133\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY1\_Msk\ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_ITATBCTR2\_ATREADY1\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01135\ \textcolor{comment}{/*\ TPI\ Integration\ ITM\ Data\ Register\ Definitions\ (FIFO1)\ */}}
\DoxyCodeLine{01136\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01137\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FIFO1\_ITM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01139\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_bytecount\_Pos\ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01140\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO1\_ITM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01142\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01143\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FIFO1\_ETM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01145\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_bytecount\_Pos\ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01146\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO1\_ETM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01148\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM2\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01149\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM2\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO1\_ITM2\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01151\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM1\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01154\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM0\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01169\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NRZVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01172\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MANCVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01173\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MANCVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_DEVID\_MANCVALID\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01175\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_PTINVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01178\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MinBufSz\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01179\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MinBufSz\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x7UL\ <<\ TPI\_DEVID\_MinBufSz\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01181\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_AsynClkIn\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01184\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NrTraceInput\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01185\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NrTraceInput\_Msk\ \ \ \ \ \ \ \ \ (0x1FUL\ }\textcolor{comment}{/*<<\ TPI\_DEVID\_NrTraceInput\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01186\ }
\DoxyCodeLine{01187\ \textcolor{comment}{/*\ TPI\ DEVTYPE\ Register\ Definitions\ */}}
\DoxyCodeLine{01188\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_SubType\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01189\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_SubType\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ TPI\_DEVTYPE\_SubType\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01190\ }
\DoxyCodeLine{01191\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_MajorType\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01192\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_MajorType\_Msk\ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ TPI\_DEVTYPE\_MajorType\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01193\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_TPI\ */}}
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\DoxyCodeLine{01196\ }
\DoxyCodeLine{01197\ \textcolor{preprocessor}{\#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01204\ }
\DoxyCodeLine{01208\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01209\ \{}
\DoxyCodeLine{01210\ \ \ \_\_IM\ \ uint32\_t\ TYPE;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01211\ \ \ \_\_IOM\ uint32\_t\ CTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01212\ \ \ \_\_IOM\ uint32\_t\ RNR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01213\ \ \ \_\_IOM\ uint32\_t\ RBAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01214\ \ \ \_\_IOM\ uint32\_t\ RASR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01215\ \ \ \_\_IOM\ uint32\_t\ RBAR\_A1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01216\ \ \ \_\_IOM\ uint32\_t\ RASR\_A1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01217\ \ \ \_\_IOM\ uint32\_t\ RBAR\_A2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01218\ \ \ \_\_IOM\ uint32\_t\ RASR\_A2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01219\ \ \ \_\_IOM\ uint32\_t\ RBAR\_A3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01220\ \ \ \_\_IOM\ uint32\_t\ RASR\_A3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01221\ \}\ \mbox{\hyperlink{struct_m_p_u___type}{MPU\_Type}};}
\DoxyCodeLine{01222\ }
\DoxyCodeLine{01223\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_RALIASES\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U}}
\DoxyCodeLine{01224\ }
\DoxyCodeLine{01225\ \textcolor{comment}{/*\ MPU\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{01226\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_IREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01227\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_IREGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_TYPE\_IREGION\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01228\ }
\DoxyCodeLine{01229\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_DREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01230\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_DREGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_TYPE\_DREGION\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01231\ }
\DoxyCodeLine{01232\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_SEPARATE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01233\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_SEPARATE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_TYPE\_SEPARATE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01234\ }
\DoxyCodeLine{01235\ \textcolor{comment}{/*\ MPU\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01236\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_PRIVDEFENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01237\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_PRIVDEFENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_CTRL\_PRIVDEFENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01238\ }
\DoxyCodeLine{01239\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_HFNMIENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01240\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_HFNMIENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_CTRL\_HFNMIENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01241\ }
\DoxyCodeLine{01242\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01243\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_CTRL\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01244\ }
\DoxyCodeLine{01245\ \textcolor{comment}{/*\ MPU\ Region\ Number\ Register\ Definitions\ */}}
\DoxyCodeLine{01246\ \textcolor{preprocessor}{\#define\ MPU\_RNR\_REGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01247\ \textcolor{preprocessor}{\#define\ MPU\_RNR\_REGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ MPU\_RNR\_REGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01248\ }
\DoxyCodeLine{01249\ \textcolor{comment}{/*\ MPU\ Region\ Base\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01250\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_ADDR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01251\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_ADDR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ MPU\_RBAR\_ADDR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01252\ }
\DoxyCodeLine{01253\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_VALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01254\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_VALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RBAR\_VALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01255\ }
\DoxyCodeLine{01256\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_REGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01257\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_REGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ MPU\_RBAR\_REGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01258\ }
\DoxyCodeLine{01259\ \textcolor{comment}{/*\ MPU\ Region\ Attribute\ and\ Size\ Register\ Definitions\ */}}
\DoxyCodeLine{01260\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_ATTRS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01261\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_ATTRS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ MPU\_RASR\_ATTRS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01262\ }
\DoxyCodeLine{01263\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_XN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01264\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_XN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RASR\_XN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01265\ }
\DoxyCodeLine{01266\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_AP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01267\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_AP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7UL\ <<\ MPU\_RASR\_AP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01268\ }
\DoxyCodeLine{01269\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_TEX\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01270\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_TEX\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7UL\ <<\ MPU\_RASR\_TEX\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01271\ }
\DoxyCodeLine{01272\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_S\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01273\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_S\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RASR\_S\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01274\ }
\DoxyCodeLine{01275\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_C\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01276\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_C\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RASR\_C\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01277\ }
\DoxyCodeLine{01278\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_B\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01279\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_B\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RASR\_B\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01280\ }
\DoxyCodeLine{01281\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_SRD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01282\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_SRD\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_RASR\_SRD\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01283\ }
\DoxyCodeLine{01284\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_SIZE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01285\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_SIZE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ <<\ MPU\_RASR\_SIZE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01286\ }
\DoxyCodeLine{01287\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01288\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_RASR\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01289\ }
\DoxyCodeLine{01291\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{01300\ }
\DoxyCodeLine{01304\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01305\ \{}
\DoxyCodeLine{01306\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1U];}
\DoxyCodeLine{01307\ \ \ \_\_IOM\ uint32\_t\ FPCCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01308\ \ \ \_\_IOM\ uint32\_t\ FPCAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01309\ \ \ \_\_IOM\ uint32\_t\ FPDSCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01310\ \ \ \_\_IM\ \ uint32\_t\ MVFR0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01311\ \ \ \_\_IM\ \ uint32\_t\ MVFR1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01312\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga479130e53a8b3c36fd8ee38b503a3911}{MVFR2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01313\ \}\ \mbox{\hyperlink{struct_f_p_u___type}{FPU\_Type}};}
\DoxyCodeLine{01314\ }
\DoxyCodeLine{01315\ \textcolor{comment}{/*\ Floating-\/Point\ Context\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01316\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_ASPEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01317\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_ASPEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_ASPEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01318\ }
\DoxyCodeLine{01319\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01320\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_LSPEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01321\ }
\DoxyCodeLine{01322\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MONRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01323\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MONRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_MONRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01324\ }
\DoxyCodeLine{01325\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_BFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01326\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_BFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_BFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01327\ }
\DoxyCodeLine{01328\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MMRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01329\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MMRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_MMRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01330\ }
\DoxyCodeLine{01331\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_HFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01332\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_HFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_HFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01333\ }
\DoxyCodeLine{01334\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_THREAD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01335\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_THREAD\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_THREAD\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01336\ }
\DoxyCodeLine{01337\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_USER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01338\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_USER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_USER\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01340\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01543\ }
\DoxyCodeLine{01544\ \textcolor{comment}{/*\ Memory\ mapping\ of\ Core\ Hardware\ */}}
\DoxyCodeLine{01545\ \textcolor{preprocessor}{\#define\ SCS\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE000E000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01551\ \textcolor{preprocessor}{\#define\ NVIC\_BASE\ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0100UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01552\ \textcolor{preprocessor}{\#define\ SCB\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0D00UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01557\ \textcolor{preprocessor}{\#define\ NVIC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((NVIC\_Type\ \ \ \ \ \ *)\ \ \ \ \ NVIC\_BASE\ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01558\ \textcolor{preprocessor}{\#define\ ITM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((ITM\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ ITM\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01568\ \textcolor{preprocessor}{\#define\ FPU\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0F30UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01573\ }
\DoxyCodeLine{01574\ }
\DoxyCodeLine{01575\ \textcolor{comment}{/*******************************************************************************}}
\DoxyCodeLine{01576\ \textcolor{comment}{\ *\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Hardware\ Abstraction\ Layer}}
\DoxyCodeLine{01577\ \textcolor{comment}{\ \ Core\ Function\ Interface\ contains:}}
\DoxyCodeLine{01578\ \textcolor{comment}{\ \ -\/\ Core\ NVIC\ Functions}}
\DoxyCodeLine{01579\ \textcolor{comment}{\ \ -\/\ Core\ SysTick\ Functions}}
\DoxyCodeLine{01580\ \textcolor{comment}{\ \ -\/\ Core\ Debug\ Functions}}
\DoxyCodeLine{01581\ \textcolor{comment}{\ \ -\/\ Core\ Register\ Access\ Functions}}
\DoxyCodeLine{01582\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{01586\ }
\DoxyCodeLine{01587\ }
\DoxyCodeLine{01588\ }
\DoxyCodeLine{01589\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ NVIC\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{01596\ }
\DoxyCodeLine{01597\ \textcolor{preprocessor}{\#ifdef\ CMSIS\_NVIC\_VIRTUAL}}
\DoxyCodeLine{01598\ \textcolor{preprocessor}{\ \ \#ifndef\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{01599\ \textcolor{preprocessor}{\ \ \ \ \#define\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE\ "{}cmsis\_nvic\_virtual.h"{}}}
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\DoxyCodeLine{01603\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPriorityGrouping\ \ \ \ \_\_NVIC\_SetPriorityGrouping}}
\DoxyCodeLine{01604\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPriorityGrouping\ \ \ \ \_\_NVIC\_GetPriorityGrouping}}
\DoxyCodeLine{01605\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_EnableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_EnableIRQ}}
\DoxyCodeLine{01606\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetEnableIRQ\ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetEnableIRQ}}
\DoxyCodeLine{01607\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_DisableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_DisableIRQ}}
\DoxyCodeLine{01608\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPendingIRQ\ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetPendingIRQ}}
\DoxyCodeLine{01609\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPendingIRQ\ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetPendingIRQ}}
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\DoxyCodeLine{01624\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetVector\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetVector}}
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\DoxyCodeLine{01638\ }
\DoxyCodeLine{01648\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \_\_NVIC\_SetPriorityGrouping(uint32\_t\ PriorityGroup)}
\DoxyCodeLine{01649\ \{}
\DoxyCodeLine{01650\ \ \ uint32\_t\ reg\_value;}
\DoxyCodeLine{01651\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
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\DoxyCodeLine{01653\ \ \ reg\_value\ \ =\ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ read\ old\ register\ configuration\ \ \ \ */}}
\DoxyCodeLine{01654\ \ \ reg\_value\ \&=\ \string~((uint32\_t)(\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga90c7cf0c490e7ae55f9503a7fda1dd22}{SCB\_AIRCR\_VECTKEY\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}}));\ \textcolor{comment}{/*\ clear\ bits\ to\ change\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{01655\ \ \ reg\_value\ \ =\ \ (reg\_value\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |}
\DoxyCodeLine{01656\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ |}
\DoxyCodeLine{01657\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (PriorityGroupTmp\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}})\ \ );\ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Insert\ write\ key\ and\ priority\ group\ */}}
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\DoxyCodeLine{01667\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core_debug_gae1de06155d072758b3453edb07d12459}{\_\_NVIC\_GetPriorityGrouping}}(\textcolor{keywordtype}{void})}
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\DoxyCodeLine{01672\ }
\DoxyCodeLine{01679\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga71227e1376cde11eda03fcb62f1b33ea}{\_\_NVIC\_EnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
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\DoxyCodeLine{01681\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01682\ \ \ \{}
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\DoxyCodeLine{01684\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01685\ \ \ \ \ \_\_COMPILER\_BARRIER();}
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\DoxyCodeLine{01698\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaaeb5e7cc0eaad4e2817272e7bf742083}{\_\_NVIC\_GetEnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
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\DoxyCodeLine{01701\ \ \ \{}
\DoxyCodeLine{01702\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
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\DoxyCodeLine{01709\ }
\DoxyCodeLine{01710\ }
\DoxyCodeLine{01717\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gae016e4c1986312044ee768806537d52f}{\_\_NVIC\_DisableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01718\ \{}
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\DoxyCodeLine{01720\ \ \ \{}
\DoxyCodeLine{01721\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01722\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{01723\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{01724\ \ \ \}}
\DoxyCodeLine{01725\ \}}
\DoxyCodeLine{01726\ }
\DoxyCodeLine{01727\ }
\DoxyCodeLine{01736\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga5a92ca5fa801ad7adb92be7257ab9694}{\_\_NVIC\_GetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01737\ \{}
\DoxyCodeLine{01738\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01739\ \ \ \{}
\DoxyCodeLine{01740\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{01741\ \ \ \}}
\DoxyCodeLine{01742\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01743\ \ \ \{}
\DoxyCodeLine{01744\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{01745\ \ \ \}}
\DoxyCodeLine{01746\ \}}
\DoxyCodeLine{01747\ }
\DoxyCodeLine{01748\ }
\DoxyCodeLine{01755\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaabefdd4b790b9a7308929938c0c1e1ad}{\_\_NVIC\_SetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01756\ \{}
\DoxyCodeLine{01757\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01758\ \ \ \{}
\DoxyCodeLine{01759\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01760\ \ \ \}}
\DoxyCodeLine{01761\ \}}
\DoxyCodeLine{01762\ }
\DoxyCodeLine{01763\ }
\DoxyCodeLine{01770\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga562a86dbdf14827d0fee8fdafb04d191}{\_\_NVIC\_ClearPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01771\ \{}
\DoxyCodeLine{01772\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01773\ \ \ \{}
\DoxyCodeLine{01774\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01775\ \ \ \}}
\DoxyCodeLine{01776\ \}}
\DoxyCodeLine{01777\ }
\DoxyCodeLine{01778\ }
\DoxyCodeLine{01787\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaa2837003c28c45abf193fe5e8d27f593}{\_\_NVIC\_GetActive}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01788\ \{}
\DoxyCodeLine{01789\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01790\ \ \ \{}
\DoxyCodeLine{01791\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IABR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{01792\ \ \ \}}
\DoxyCodeLine{01793\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01794\ \ \ \{}
\DoxyCodeLine{01795\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{01796\ \ \ \}}
\DoxyCodeLine{01797\ \}}
\DoxyCodeLine{01798\ }
\DoxyCodeLine{01799\ }
\DoxyCodeLine{01809\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga505338e23563a9c074910fb14e7d45fd}{\_\_NVIC\_SetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ priority)}
\DoxyCodeLine{01810\ \{}
\DoxyCodeLine{01811\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01812\ \ \ \{}
\DoxyCodeLine{01813\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IP[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{01814\ \ \ \}}
\DoxyCodeLine{01815\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01816\ \ \ \{}
\DoxyCodeLine{01817\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHP[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{01818\ \ \ \}}
\DoxyCodeLine{01819\ \}}
\DoxyCodeLine{01820\ }
\DoxyCodeLine{01821\ }
\DoxyCodeLine{01831\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaeb9dc99c8e7700668813144261b0bc73}{\_\_NVIC\_GetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01832\ \{}
\DoxyCodeLine{01833\ }
\DoxyCodeLine{01834\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01835\ \ \ \{}
\DoxyCodeLine{01836\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IP[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{01837\ \ \ \}}
\DoxyCodeLine{01838\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01839\ \ \ \{}
\DoxyCodeLine{01840\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHP[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{01841\ \ \ \}}
\DoxyCodeLine{01842\ \}}
\DoxyCodeLine{01843\ }
\DoxyCodeLine{01844\ }
\DoxyCodeLine{01856\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gadb94ac5d892b376e4f3555ae0418ebac}{NVIC\_EncodePriority}}\ (uint32\_t\ PriorityGroup,\ uint32\_t\ PreemptPriority,\ uint32\_t\ SubPriority)}
\DoxyCodeLine{01857\ \{}
\DoxyCodeLine{01858\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{01859\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{01860\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{01861\ }
\DoxyCodeLine{01862\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{01863\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{01864\ }
\DoxyCodeLine{01865\ \ \ \textcolor{keywordflow}{return}\ (}
\DoxyCodeLine{01866\ \ \ \ \ \ \ \ \ \ \ \ ((PreemptPriority\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL))\ <<\ SubPriorityBits)\ |}
\DoxyCodeLine{01867\ \ \ \ \ \ \ \ \ \ \ \ ((SubPriority\ \ \ \ \ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL)))}
\DoxyCodeLine{01868\ \ \ \ \ \ \ \ \ \ );}
\DoxyCodeLine{01869\ \}}
\DoxyCodeLine{01870\ }
\DoxyCodeLine{01871\ }
\DoxyCodeLine{01883\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga3387607fd8a1a32cccd77d2ac672dd96}{NVIC\_DecodePriority}}\ (uint32\_t\ Priority,\ uint32\_t\ PriorityGroup,\ uint32\_t*\ \textcolor{keyword}{const}\ pPreemptPriority,\ uint32\_t*\ \textcolor{keyword}{const}\ pSubPriority)}
\DoxyCodeLine{01884\ \{}
\DoxyCodeLine{01885\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{01886\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{01887\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{01888\ }
\DoxyCodeLine{01889\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{01890\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{01891\ }
\DoxyCodeLine{01892\ \ \ *pPreemptPriority\ =\ (Priority\ >>\ SubPriorityBits)\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL);}
\DoxyCodeLine{01893\ \ \ *pSubPriority\ \ \ \ \ =\ (Priority\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ )\ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL);}
\DoxyCodeLine{01894\ \}}
\DoxyCodeLine{01895\ }
\DoxyCodeLine{01896\ }
\DoxyCodeLine{01906\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0df355460bc1783d58f9d72ee4884208}{\_\_NVIC\_SetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ vector)}
\DoxyCodeLine{01907\ \{}
\DoxyCodeLine{01908\ \ \ uint32\_t\ vectors\ =\ (uint32\_t\ )\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{01909\ \ \ (*\ (\textcolor{keywordtype}{int}\ *)\ (vectors\ +\ ((int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET)\ *\ 4))\ =\ vector;}
\DoxyCodeLine{01910\ \ \ \textcolor{comment}{/*\ ARM\ Application\ Note\ 321\ states\ that\ the\ M4\ does\ not\ require\ the\ architectural\ barrier\ */}}
\DoxyCodeLine{01911\ \}}
\DoxyCodeLine{01912\ }
\DoxyCodeLine{01913\ }
\DoxyCodeLine{01922\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga44b665d2afb708121d9b10c76ff00ee5}{\_\_NVIC\_GetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01923\ \{}
\DoxyCodeLine{01924\ \ \ uint32\_t\ vectors\ =\ (uint32\_t\ )\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{01925\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(*\ (\textcolor{keywordtype}{int}\ *)\ (vectors\ +\ ((int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET)\ *\ 4));}
\DoxyCodeLine{01926\ \}}
\DoxyCodeLine{01927\ }
\DoxyCodeLine{01928\ }
\DoxyCodeLine{01933\ \_\_NO\_RETURN\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0d9aa2d30fa54b41eb780c16e35b676c}{\_\_NVIC\_SystemReset}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{01934\ \{}
\DoxyCodeLine{01935\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ all\ outstanding\ memory\ accesses\ included}}
\DoxyCodeLine{01936\ \textcolor{comment}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ buffered\ write\ are\ completed\ before\ reset\ */}}
\DoxyCodeLine{01937\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \ =\ (uint32\_t)((0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ \ \ \ |}
\DoxyCodeLine{01938\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ |}
\DoxyCodeLine{01939\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaae1181119559a5bd36e62afa373fa720}{SCB\_AIRCR\_SYSRESETREQ\_Msk}}\ \ \ \ );\ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Keep\ priority\ group\ unchanged\ */}}
\DoxyCodeLine{01940\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ completion\ of\ memory\ access\ */}}
\DoxyCodeLine{01941\ }
\DoxyCodeLine{01942\ \ \ \textcolor{keywordflow}{for}(;;)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ wait\ until\ reset\ */}}
\DoxyCodeLine{01943\ \ \ \{}
\DoxyCodeLine{01944\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gabd585ddc865fb9b7f2493af1eee1a572}{\_\_NOP}}();}
\DoxyCodeLine{01945\ \ \ \}}
\DoxyCodeLine{01946\ \}}
\DoxyCodeLine{01947\ }
\DoxyCodeLine{01949\ }
\DoxyCodeLine{01950\ }
\DoxyCodeLine{01951\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ MPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{01952\ }
\DoxyCodeLine{01953\ \textcolor{preprocessor}{\#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{01954\ }
\DoxyCodeLine{01955\ \textcolor{preprocessor}{\#include\ "{}mpu\_armv7.h"{}}}
\DoxyCodeLine{01956\ }
\DoxyCodeLine{01957\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01958\ }
\DoxyCodeLine{01959\ }
\DoxyCodeLine{01960\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ FPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{01967\ }
\DoxyCodeLine{01976\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga6bcad99ce80a0e7e4ddc6f2379081756}{SCB\_GetFPUType}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{01977\ \{}
\DoxyCodeLine{01978\ \ \ uint32\_t\ mvfr0;}
\DoxyCodeLine{01979\ }
\DoxyCodeLine{01980\ \ \ mvfr0\ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabc7c93f2594e85ece1e1a24f10591428}{FPU}}-\/>MVFR0;}
\DoxyCodeLine{01981\ \ \ \textcolor{keywordflow}{if}\ \ \ \ \ \ ((mvfr0\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95008f205c9d25e4ffebdbdc50d5ae44}{FPU\_MVFR0\_Single\_precision\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga3f2c8c6c759ffe70f548a165602ea901}{FPU\_MVFR0\_Double\_precision\_Msk}}))\ ==\ 0x020U)}
\DoxyCodeLine{01982\ \ \ \{}
\DoxyCodeLine{01983\ \ \ \ \ \textcolor{keywordflow}{return}\ 1U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Single\ precision\ FPU\ */}}
\DoxyCodeLine{01984\ \ \ \}}
\DoxyCodeLine{01985\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01986\ \ \ \{}
\DoxyCodeLine{01987\ \ \ \ \ \textcolor{keywordflow}{return}\ 0U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ No\ FPU\ */}}
\DoxyCodeLine{01988\ \ \ \}}
\DoxyCodeLine{01989\ \}}
\DoxyCodeLine{01990\ }
\DoxyCodeLine{01991\ }
\DoxyCodeLine{01993\ }
\DoxyCodeLine{01994\ }
\DoxyCodeLine{01995\ }
\DoxyCodeLine{01996\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ \ SysTick\ function\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02003\ }
\DoxyCodeLine{02004\ \textcolor{preprocessor}{\#if\ defined\ (\_\_Vendor\_SysTickConfig)\ \&\&\ (\_\_Vendor\_SysTickConfig\ ==\ 0U)}}
\DoxyCodeLine{02005\ }
\DoxyCodeLine{02017\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gae4e8f0238527c69f522029b93c8e5b78}{SysTick\_Config}}(uint32\_t\ ticks)}
\DoxyCodeLine{02018\ \{}
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